How to simulate PCIE / IEEE path on PCB + Everything you need to know | Explained by Bert Simonovich

Setting up simulation and explaining everything essential you need to know about channel simulation such PCIE or IEEE. Thank you very much Bert Simonovich DesignCon: Use 15% DesignCon 2024 Discount coupon: FED24 Other Links: - Bert’s Linked In: - Small Things Damaging Your High Speed Signals (with Bert Simonovich): - FEDEVEL courses: Chapters: 00:00 What is this video about 00:53 What is channel and why to simulate it 06:33 Why is loss important 14:25 Stackup 15:21 Dielectric properties Df Dk 21:47 Copper roughness 27:34 Construction tables and stackup 33:05 10 layer stackup example 38:30 When start worrying about stackup details 48:03 Copper Roughness models 57:53 Filling up Stackup into Polar software 1:03:53 Setting up Dk and roughness 1:06:46 Calculating Loss of a transmission line for stackup in Polar 1:09:05 Saving model of transmission line 1:20:29 Creating models of VIAs 1:33:20 Dielectric anisotropy 1:38:52 DesignCon 1:42:41 Creating and setting up simulation 1:51:11 Simulation and results 1:54:04 Comparing good and bad PCB material results 1:57:28 COM - Channel Operating Margin 1:59:07 Setting up COM simulation 2:02:57 COM results ------------------------------------------------------ Would you like to support me? It’s simple: - Sign up for online courses hosted on our platform: - You can also support me through Patreon: - FEDEVEL Discord: It is much appreciated. Thank you, - Robert