Support for Non-Coherent I/O Devices in RISC-V- Greg Favor & David Kruckemyer, Ventana Micro Systems

Support for Non-Coherent I/O Devices in RISC-V - Greg Favor & David Kruckemyer, Ventana Micro Systems The current RISC-V ISA privilege specification only defines a broad physical memory attribute (PMA) mechanism to implement non-cacheable memory regions for any non-coherent I/O devices. While this is an acceptable approach in an embedded world, it is not sufficient for modern-day systems where the number of programmable PMAs will not scale. On other hand, having a fully coherent system is not always feasible due to design costs in spite of performance advantages. Thus, any platform with non- coherent I/O devices relies on the software managed coherency, a widely adopted approach in today’s industry. The software can manage coherency either by accessing the memory in such a way that it is never cached or use cache maintenance instructions for cacheable memory. The Svpbmt(Page Based Memory Type) extension was recently proposed to provide a solution to the first approach while a set of CMO(Zicbom, Zicboz, and Z